#pragma ONCE /* GENERAL DEFINITIONS FOR HC08 rev 1.0 */ /* * ANSI C standard types setting for the HC08 family * char=8 bit;short=int=16 bit;long=32 bit * Types are unsigned */ #define boolean unsigned char #define U8 unsigned char #define VU8 volatile unsigned char #define U16 unsigned short #define VU16 volatile unsigned short #define U32 unsigned long #define VU32 volatile unsigned long /* GENERAL section*/ #define TRUE 1 #define FALSE 0 #define NONE 0 #define SET 1 #define CLEAR 0 #define ON 1 #define OFF 0 #define ENABLE 1 #define DISABLE 0 #define OK 1 #define ERROR 0 #define BIT0 0x01 #define BIT1 0x02 #define BIT2 0x04 #define BIT3 0x08 #define BIT4 0x10 #define BIT5 0x20 #define BIT6 0x40 #define BIT7 0x80 #define BIT0_SET 1 #define BIT1_SET 2 #define BIT2_SET 4 #define BIT3_SET 8 #define BIT4_SET 0x10 #define BIT5_SET 0x20 #define BIT6_SET 0x40 #define BIT7_SET 0x80 #define BIT0_CLEAR 0xfe #define BIT1_CLEAR 0xfd #define BIT2_CLEAR 0xfb #define BIT3_CLEAR 0xf7 #define BIT4_CLEAR 0xef #define BIT5_CLEAR 0xdf #define BIT6_CLEAR 0xbf #define BIT7_CLEAR 0x7f /* SYSTEM Section */ #define VCO_FREQ_MULTIPL_LOW (U8)( 900 & 0x00FF ) #define VCO_FREQ_MULTIPL_HI (U8)( (900 & 0x0F00) >> 8 ) #define VCO_RANGE_SELECT 192 #define PLL_REF_DIVIDER_VAL 0x1 #define EDGE_ALIGN_MODE_ENABLE BIT7 #define CENTER_ALIGN_MODE_ENABLE 0 #define PWM_BOTTOM_SIDE_NEGATIVE BIT6 #define PWM_BOTTOM_SIDE_POSITIVE 0 #define PWM_TOP_SIDE_NEGATIVE BIT5 #define PWM_TOP_SIDE_POSITIVE 0 #define PWM_SIX_INDE BIT4 #define PWM_THREE_COMP 0 #define LVI_ENABLE_MODULE_RESET BIT3 #define LVI_DISABLE_MODULE_RESET 0 #define LVI_MODULE_POWER_ENABLE BIT2 #define LVI_MODULE_POWER_DISABLE 0 /* CONFIG1 */ #define MOR_STOP_ENABLE BIT1 #define MOR_STOP_DISABLE 0 #define DISABLE_COP_MODULE BIT0 #define ENABLE_COP_MODULE 0 /* BREAK MODULE */ #define BREAK_INT_IN_WAIT_FLAG BIT1 #define BREAK_MODE_ENABLE BIT7 #define BREAK_MODE_DISABLE 0 #define BREAK_ADDR_MATCH_FLAG BIT6 /* CONFIG2 */ #define OSCI_IN_STOP_ENABLE BIT1 #define OSCI_IN_STOP_DISABLE 0 #define SCI_INTERNAL_BUS_CLOCK BIT0 #define SCI_EXTERNAL_OSCI_CLOCK 0 /* CONFIG1 */ #define COP_TIMOUT_SHORT BIT7 #define COP_TIMOUT_LONG 0 #define LVI_ENABLE_IN_STOP BIT6 #define LVI_DISABLE_IN_STOP 0 #define LVI_RESET_DISABLE BIT5 #define LVI_RESET_ENABLE 0 #define LVI_POWERD_DISABLE BIT4 #define LVI_POWERD_ENABLE 0 #define LVI_IN_5_V BIT3 #define LVI_IN_3_V 0 #define FAST_RECOVERY_FROM_STOP BIT2 #define SLOW_RECOVERY_FROM_STOP 0 #define CONFIG1_STOPE_ENABLE BIT1 #define CONFIG1_STOP_DISABLE 0 /* END CONFIG1 */ /* MORA */ #define ENABLE_ROM_SECURITY BIT6 #define DISABLE_ROM_SECURITY 0 /* END MORA */ /* MORB */ #define ENABLE_EEPROM_SECURITY BIT5 #define DISABLE_EEPROM_SECURITY 0 /* END MORB */ /* SCI */ #define SCI_RETRY_NUM 100 /*SCC1*/ #define SCI_LOOP_ENABLE BIT7 #define SCI_LOOP_DISABLE 0 #define ENABLE_SCI BIT6 #define DISABLE_SCI 0 #define SCI_TRANSMIT_INVERTED BIT5 #define SCI_TRANSMIT_UNINVERTED 0 #define SCI_9_BIT_DATA BIT4 #define SCI_8_BIT_DATA 0 #define SCI_ADDRESS_WAKEUP BIT3 #define SCI_IDLE_WAKEUP 0 #define SCI_IDLE_AFTER_STOP BIT2 #define SCI_IDLE_AFTER_START 0 #define SCI_ENABLE_PARITY BIT1 #define SCI_DISABLE_PARITY 0 #define SCI_ODD_PARITY BIT0 #define SCI_EVEN_PARITY 0 /*END SCC1*/ /*SCC2 INTERRUPTS*/ #define SCI_INT_TRAN_ENABLE BIT7 #define SCI_INT_TRAN_DISABLE 0 #define SCI_Tx_INT_ENABLE BIT7 #define SCI_Tx_INT_DISABLE 0 #define SCI_INT_TRAN_COMP_ENABLE BIT6 #define SCI_INT_TRAN_COMP_DISABLE 0 #define SCI_INT_REC_ENABLE BIT5 #define SCI_INT_REC_DISABLE 0 #define SCI_Rx_INT_ENABLE BIT5 #define SCI_Rx_INT_DISABLE 0 #define SCI_INT_IDLE_ENABLE BIT4 #define SCI_INT_IDLE_DISABLE 0 #define SCI_TRANSMITTER_ENABLE BIT3 #define SCI_TRANSMITTER_DISABLE 0 #define SCI_RECEIVER_ENABLE BIT2 #define SCI_RECEIVER_DISABLE 0 #define SCI_RWU_STANDBY_STAT BIT1 #define SCI_RWU_NORMAL 0 #define SCI_SEND_BREAK_ENABLE BIT0 #define SCI_SEND_BREAK_DISABLE 0 /*END SCC2 */ /*SCC3*/ /*DMA*/ #define SCI_DMA_FOR_REC_ENABLE BIT5 #define SCI_DMA_FOR_REC_DISABLE 0 #define SCI_DMA_FOR_TRAN_ENABLE BIT4 #define SCI_DMA_FOR_TRAN_DISABLE 0 /*INTERRUPTS*/ #define SCI_INT_REC_OVERUN_ENABLE BIT3 #define SCI_INT_REC_OVERUN_DISABLE 0 #define SCI_INT_REC_NOISE_ENABLE BIT2 #define SCI_INT_REC_NOISE_DISABLE 0 #define SCI_INT_REC_FRAME_ENABLE BIT1 #define SCI_INT_REC_FRAME_DISABLE 0 #define SCI_INT_REC_PARITY_ENABLE BIT0 #define SCI_INT_REC_PARITY_DISABLE 0 /*END SCC3*/ /*SCS1*/ #define SCI_TX_EMPTY_FLAG BIT7 #define SCI_TX_COMPLETE_FLAG BIT6 #define SCI_RX_FULL_FLAG BIT5 #define SCI_RX_IDLE_FLAG BIT4 #define SCI_RX_OVERRUN_FLAG BIT3 #define SCI_RX_NIOSE_FLAG BIT2 #define SCI_RX_FRAME_FLAG BIT1 #define SCI_RX_PARITY_FLAG BIT0 /*END SCS1*/ /*SCS2*/ #define SCI_RX_BREAK_FLAG BIT1 #define SCI_RX_PROGRES_FLAG BIT0 /*SCBR*/ #define SCI_PD_DIV_BY_1 0 #define SCI_PD_DIV_BY_3 0x10 #define SCI_PD_DIV_BY_4 0x20 #define SCI_PD_DIV_BY_13 0x30 #define SCI_BD_DIV_BY_1 0 #define SCI_BD_DIV_BY_2 0x01 #define SCI_BD_DIV_BY_4 0x02 #define SCI_BD_DIV_BY_8 0x03 #define SCI_BD_DIV_BY_16 0x04 #define SCI_BD_DIV_BY_32 0x05 #define SCI_BD_DIV_BY_64 0x06 #define SCI_BD_DIV_BY_128 0x07 /*END SCBR*/ /* SPI */ #define SPI_RETRY_NUM 100 #define SPI_MASTER 1 #define SPI_SLAVE 0 /* SPCR */ #define SPI_Rx_INT_ENABLE BIT7 #define SPI_Rx_INT_DISABLE 0 #define SPI_DMA_FLAG BIT6 #define SPI_IN_MASTER_MODE BIT5 #define SPI_IN_SLAVE_MODE 0 #define SPI_CLOCK_POLARITY_HIGH BIT4 #define SPI_CLOCK_POLARITY_LOW 0 #define SPI_CLOCK_PHASE_HIGH BIT3 #define SPI_CLOCK_PHASE_LOW 0 #define SPI_WIRED_OPEN_DRAIN BIT2 #define SPI_NORMAL_PUSH_PULL 0 #define ENABLE_SPI BIT1 #define DISABLE_SPI 0 #define SPI_Tx_INT_ENABLE BIT0 #define SPI_Tx_INT_DISABLE 0 /* END */ /* SPSCR */ #define SPI_RECEIVE_FULL_FLAG BIT7 #define SPI_ERROR_INT_ENABLE BIT6 #define SPI_ERROR_INT_DISABLE 0 #define SPI_OVERFLOW_FLAG BIT5 #define SPI_MODE_FAULT_FLAG BIT4 #define SPI_TASMMITER_EMPTY_FLAG BIT3 #define SPI_MODE_FAULT_ENABLE BIT2 #define SPI_MODE_FAULT_DISABLE 0 #define SPI_BD_2 0 #define SPI_BD_8 0x01 #define SPI_BD_32 0x02 #define SPI_BD_128 0x03 /* END */ #define SPI_LOW_POLARITY_LOW_PHASE (SPI_CLOCK_POLARITY_LOW | SPI_CLOCK_PHASE_LOW) #define SPI_LOW_POLARITY_HIGH_PHASE (SPI_CLOCK_POLARITY_LOW | SPI_CLOCK_PHASE_HIGH) #define SPI_HIGH_POLARITY_LOW_PHASE (SPI_CLOCK_POLARITY_HIGH | SPI_CLOCK_PHASE_LOW) #define SPI_HIGH_POLARITY_HIGH_PHASE (SPI_CLOCK_POLARITY_HIGH | SPI_CLOCK_PHASE_HIGH) /* END */ #define PLL_INTERRUPT_ENABLED BIT7 #define PLL_INTERRUPT_DISABLED 0 #define PLL_INTERRUPT_FLAG_SET BIT6 #define PLL_ON BIT5 #define PLL_OFF 0 #define PLL_VCO_ENABLE BIT4 #define PLL_VCO_DISABLE 0 #define PLL_LOCKED 1 #define PLL_UNLOCKED 0 #define PLL_AUTOMATIC_CONTROL BIT7 #define PLL_MANUAL_CONTROL 0 #define PLL_VCO_LOOK BIT6 #define PLL_ON_TRACKING_MODE BIT5 #define PLL_ON_ACQUISITION_MODE 0 #define STATUS_BITS_CLEARABLE BIT7 #define STATUS_BITS_NOT_CLEARABLE 0 /* IRQ */ #define IRQ_FALLING_EDGE_AND_LEVEL BIT0 #define IRQ_FALLING_EDGE_ONLY 0 #define IRQ1_DISABLE BIT1 #define IRQ1_ENABLE 0 #define IRQ_CLEAR_LATCH BIT2 #define IRQ1_EVENT_SET BIT3 /* GENERAL DEFINITIONS FOR HC08 PORTS */ #define PORT_A 0 #define PORT_B 1 #define PORT_C 2 #define PORT_D 3 #define PORT_E 4 #define PORT_F 5 #define PORT_G 6 #define PORT_H 7 #define MAX_PORTS 6 #define INPUT_PORT 0x0 #define OUTPUT_PORT 0xff #define INPUT 0x0 #define OUTPUT 0x1 #define PIN_INPUT 0x0 #define PIN_OUTPUT 0x1 #define PIN_PU_DISABLE 0x0 #define PIN_PU_ENABLE 0x1 #define PIN0 0x01 #define PIN1 0x02 #define PIN2 0x04 #define PIN3 0x08 #define PIN4 0x10 #define PIN5 0x20 #define PIN6 0x40 #define PIN7 0x80 /* GENERAL DEFINITIONS FOR HC08 TIMERS */ #define TIMER_A0_INCREMENT_COMPARE_VAL 184 /* GENERAL DEFINITIONS FOR HC08 PWM */ #define TIMER_CHANNELx_FLAG BIT7 #define TIMER_CHAN_INT_ENABLE BIT6 #define TIMER_CHAN_INT_DISABLE 0 #define TIMER_PIN_TOGGLE (BIT4 | BIT2) #define TIMER_PIN_CLEAR (BIT4 | BIT3) #define TIMER_PIN_SET (BIT4 | BIT3 | BIT2) #define TIMER_BUFFERD_PIN_TOGGLE (BIT5 | BIT4 | BIT2) #define TIMER_BUFFERD_PIN_CLEAR (BIT5 | BIT4 | BIT3) #define TIMER_BUFFERD_PIN_SET (BIT5 | BIT4 | BIT3 | BIT2) #define TIMER_PORT_HIGH 0 #define TIMER_PORT_LOW (BIT4) #define TIMER_PIN_CAPT_RISING (BIT2) #define TIMER_PIN_CAPT_FALL (BIT3) #define TIMER_PIN_CAPT_FALL_RISING (BIT2 | BIT3) #define TIMER_TOGGLE_ON_OVERFLOW BIT1 #define TIMER_NO_TOGGLE_ON_OVERFLOW 0 #define TIMER_A 1 #define TIMER_B 2 #define TIMER_CHANNEL_0 0 #define TIMER_CHANNEL_1 1 #define TIMER_CHANNEL_2 2 #define TIMER_CHANNEL_3 3 #define TIMER_CHANNEL_4 4 #define TIMER_CHANNEL_5 5 #define CLEAR_TIMER_MODE_SELECT 0xc3 #define TIMER_OVERFLOW_FLAG BIT7 #define TIMER_OVERFLOW_INT_ENABLE BIT6 #define TIMER_OVERFLOW_INT_DISABLE 0 #define TIMER_STOP_COUNTE BIT5 #define TIMER_RESET_BIT BIT4 #define INTERNAL_BUS_CLK 0 #define BUS_CLK_DIV_BY_1 0 #define BUS_CLK_DIV_BY_2 0x01 #define BUS_CLK_DIV_BY_4 0x02 #define BUS_CLK_DIV_BY_8 0x03 #define BUS_CLK_DIV_BY_16 0x04 #define BUS_CLK_DIV_BY_32 0x05 #define BUS_CLK_DIV_BY_64 0x06 #define TIMER_EXT_CLK 0x07 /* PIT */ #define PIT_OVERFLOW_FLAG BIT7 #define PIT_OVERFLOW_INT_ENABLE BIT6 #define PIT_OVERFLOW_INT_DISABLE 0 #define PIT_STOP_COUNTE BIT5 #define PIT_RESET BIT4 /* END PIT */ /* TIM */ #define TIM_OVERFLOW_FLAG BIT7 #define TIM_OVERFLOW_INT_ENABLE BIT6 #define TIM_OVERFLOW_INT_DISABLE 0 #define TIM_STOP_COUNTE BIT5 #define TIM_RESET BIT4 /* END TIM */ /* TBM */ #define CRYSTAL_DIV_BY_32768 0 #define CRYSTAL_DIV_BY_8192 0x10 #define CRYSTAL_DIV_BY_2048 0x20 #define CRYSTAL_DIV_BY_128 0x30 #define CRYSTAL_DIV_BY_64 0x40 #define CRYSTAL_DIV_BY_32 0x50 #define CRYSTAL_DIV_BY_16 0x60 #define CRYSTAL_DIV_BY_8 0x70 #define ENABLE_TBM BIT1 #define DISABLE_TBM 0 #define ENABLE_TBM_INTERRUPT BIT2 #define DISABLE_TBM_INTERRUPT 0 #define SET_TACK BIT3 /*ADC Section*/ #define ATD0 0 #define ATD1 0x01 #define ATD2 0x02 #define ATD3 0x03 #define ATD4 0x04 #define ATD5 0x05 #define ATD6 0x06 #define ATD7 0x07 #define ATD8 0x08 #define ATD9 0x09 #define ATD10 0x0a #define ATD11 0x0b #define ATD12 0x0c #define ATD13 0x0d #define ATD14 0x0e #define ATD_VREFHI 0x1d #define ATD_VREFLOW 0x1e #define ADC_OFF 0x1f #define ADC_CHANNEL_SELECT_BITS 0x1f #define ADC_CLK_DIV_1 0x0 #define ADC_CLK_DIV_2 0x20 #define ADC_CLK_DIV_4 0x40 #define ADC_CLK_DIV_8 0x60 #define ADC_CLK_DIV_16 0x80 #define ADC_PRESCALER_SELECT_BITS 0xE0 #define ADC_CONVER_COMPLETE 0x80 #define ADC_CONTINUOUS_CONVERSION 0x20 #define ADC_ONE_CONVERSION 0 #define DISABLE_ADC_INTERRUPT 0 #define ENABLE_ADC_INTERRUPT 0x40 #define ADC_INPUT_CLK_BUS 0x10 #define ADC_INPUT_CLK_CRYSTAL 0 #define ADC_RESULT_8_BIT 0 #define ADC_RESULT_RIGHT 0x04 #define ADC_RESULT_LEFT_UNSING 0x08 #define ADC_RESULT_LEFT_SING 0x0c #define ADC_RESULT_MODE_BIT 0x0c #define ENABLE_KBI_INT_0 BIT0 #define DISABLE_KBI_INT_0 0 #define ENABLE_KBI_INT_1 BIT1 #define DISABLE_KBI_INT_1 0 #define ENABLE_KBI_INT_2 BIT2 #define DISABLE_KBI_INT_2 0 #define ENABLE_KBI_INT_3 BIT3 #define DISABLE_KBI_INT_3 0 #define ENABLE_KBI_INT_4 BIT4 #define DISABLE_KBI_INT_4 0 #define ENABLE_KBI_INT_5 BIT5 #define DISABLE_KBI_INT_5 0 #define ENABLE_KBI_INT_6 BIT6 #define DISABLE_KBI_INT_6 0 #define ENABLE_KBI_INT_7 BIT7 #define DISABLE_KBI_INT_7 0 #define KBI_INT_ON_FALLING_OR_LOW BIT0 #define KBI_INT_ON_FALLING 0 #define ENABLE_KBI_INT 0 #define DISABLE_KBI_INT BIT1 #define KBI_INT_FLAG BIT3 #define KBI_ACKNOWLEDGE BIT2 #define KBI_INT0 BIT0 #define KBI_INT1 BIT1 #define KBI_INT2 BIT2 #define KBI_INT3 BIT3 #define KBI_INT4 BIT4 #define KBI_INT5 BIT5 #define KBI_INT6 BIT6 #define KBI_INT7 BIT7