#pragma ONCE #define MC68HC908GP32 /* IO DEFINITIONS FOR MC68HC908GP32 - rev 3.0 */ /* PORTS section */ #define PTA (*(volatile unsigned char*)(0x00)) /* port A */ #define pPTA (volatile unsigned char*)(0x00) /* port A */ #define PTB (*(volatile unsigned char*)(0x01)) /* port B */ #define pPTB (volatile unsigned char*)(0x01) /* port B */ #define PTC (*(volatile unsigned char*)(0x02)) /* port C */ #define pPTC (volatile unsigned char*)(0x02) /* port C */ #define PTD (*(volatile unsigned char*)(0x03)) /* port D */ #define pPTD (volatile unsigned char*)(0x03) /* port D */ #define DDRA (*(volatile unsigned char*)(0x04)) /* data direction port A */ #define pDDRA (volatile unsigned char*)(0x04) /* data direction port A */ #define DDRB (*(volatile unsigned char*)(0x05)) /* data direction port B */ #define pDDRB (volatile unsigned char*)(0x05) /* data direction port B */ #define DDRC (*(volatile unsigned char*)(0x06)) /* data direction port C */ #define pDDRC (volatile unsigned char*)(0x06) /* data direction port C */ #define DDRD (*(volatile unsigned char*)(0x07)) /* data direction port D */ #define pDDRD (volatile unsigned char*)(0x07) /* data direction port D */ #define PTE (*(volatile unsigned char*)(0x08)) /* port E */ #define pPTE (volatile unsigned char*)(0x08) /* port E */ #define RES1 (*(volatile unsigned char*)(0x09)) /* Unimplemented */ #define pRES1 (volatile unsigned char*)(0x09) /* Unimplemented */ #define RES2 (*(volatile unsigned char*)(0x0A)) /* Unimplemented */ #define pRES2 (volatile unsigned char*)(0x0A) /* Unimplemented */ #define RES3 (*(volatile unsigned char*)(0x0B)) /* Unimplemented */ #define pRES3 (volatile unsigned char*)(0x0B) /* Unimplemented */ #define DDRE (*(volatile unsigned char*)(0x0C)) /* data direction port E */ #define pDDRE (volatile unsigned char*)(0x0C) /* data direction port E */ #define PTAPUE (*(volatile unsigned char*)(0x0D)) /* Port A input pullup Enable */ #define pPTAPUE (volatile unsigned char*)(0x0D) /* Port A input pullup Enable */ #define PTCPUE (*(volatile unsigned char*)(0x0E)) /* Port C input pullup Enable */ #define pPTCPUE (volatile unsigned char*)(0x0E) /* Port C input pullup Enable */ #define PTDPUE (*(volatile unsigned char*)(0x0F)) /* Port D input pullup Enable */ #define pPTDPUE (volatile unsigned char*)(0x0F) /* Port D input pullup Enable */ /* SPI section */ #define SPCR (*(volatile unsigned char*)(0x10)) /* SPI control register */ #define pSPCR (volatile unsigned char*)(0x10) /* SPI control register */ #define SPSCR (*(volatile unsigned char*)(0x11)) /* SPI control/status register */ #define pSPSCR (volatile unsigned char*)(0x11) /* SPI control/status register */ #define SPDR (*(volatile unsigned char*)(0x12)) /* SPI data register */ #define pSPDR (volatile unsigned char*)(0x12) /* SPI data register */ /* SCI section */ #define SCC1 (*(volatile unsigned char*)(0x13)) /* SCI control register 1 */ #define pSCC1 (volatile unsigned char*)(0x13) /* SCI control register 1 */ #define SCC2 (*(volatile unsigned char*)(0x14)) /* SCI control register 2 */ #define pSCC2 (volatile unsigned char*)(0x14) /* SCI control register 2 */ #define SCC3 (*(volatile unsigned char*)(0x15)) /* SCI control register 3 */ #define pSCC3 (volatile unsigned char*)(0x15) /* SCI control register 3 */ #define SCS1 (*(volatile unsigned char*)(0x16)) /* SCI status register 1 */ #define pSCS1 (volatile unsigned char*)(0x16) /* SCI status register 1 */ #define SCS2 (*(volatile unsigned char*)(0x17)) /* SCI status register 2 */ #define pSCS2 (volatile unsigned char*)(0x17) /* SCI status register 2 */ #define SCDR (*(volatile unsigned char*)(0x18)) /* SCI data register */ #define pSCDR (volatile unsigned char*)(0x18) /* SCI data register */ #define SCBR (*(volatile unsigned char*)(0x19)) /* SCI baud rate */ #define pSCBR (volatile unsigned char*)(0x19) /* SCI baud rate */ /* KEYBOARD section */ #define INTKBSCR (*(volatile unsigned char*)(0x1A)) /* Keyboard status and control register */ #define pINTKBSCR (volatile unsigned char*)(0x1A) /* Keyboard status and control register */ #define INTKBIER (*(volatile unsigned char*)(0x1B)) /* Keyboard interrupt Enable */ #define pINTKBIER (volatile unsigned char*)(0x1B) /* Keyboard interrupt Enable */ #define TBCR (*(volatile unsigned char*)(0x1C)) /* Time base module control */ #define pTBCR (volatile unsigned char*)(0x1C) /* Time base module control */ /* INTERRUPT section */ #define ISCR (*(volatile unsigned char*)(0x1D)) /* IRQ control/status register */ #define pISCR (volatile unsigned char*)(0x1D) /* IRQ control/status register */ /* CONFIGURATION section */ #define CONFIG2 (*(volatile unsigned char*)(0x1E)) /* Configuration register 2 */ #define pCONFIG2 (volatile unsigned char*)(0x1E) /* Configuration register 2 */ #define CONFIG1 (*(volatile unsigned char*)(0x1F)) /* Configuration register 1 */ #define pCONFIG1 (volatile unsigned char*)(0x1F) /* Configuration register 1 */ /* A TIMER section */ #define TASC (*(volatile unsigned char*)(0x20)) /* timer A status/ctrl register */ #define pTASC (volatile unsigned char*)(0x20) /* timer A status/ctrl register */ #define TACNTHL (*(volatile unsigned short*)(0x21)) /* timer A counter high and low */ #define pTACNTHL (volatile unsigned short*)(0x21) /* timer A counter high and low */ #define TACNTH (*(volatile unsigned char*)(0x21)) /* timer A counter high */ #define pTACNTH (volatile unsigned char*)(0x21) /* timer A counter high */ #define TACNTL (*(volatile unsigned char*)(0x22)) /* timer A counter low */ #define pTACNTL (volatile unsigned char*)(0x22) /* timer A counter low */ #define TAMODHL (*(volatile unsigned short*)(0x23)) /* timer A modulo high and low */ #define pTAMODHL (volatile unsigned short*)(0x23) /* timer A modulo high and low */ #define TAMODH (*(volatile unsigned char*)(0x23)) /* timer A modulo high */ #define pTAMODH (volatile unsigned char*)(0x23) /* timer A modulo high */ #define TAMODL (*(volatile unsigned char*)(0x24)) /* timer A modulo low */ #define pTAMODL (volatile unsigned char*)(0x24) /* timer A modulo low */ #define TASC0 (*(volatile unsigned char*)(0x25)) /* timer A channel 0 status/ctrl */ #define pTASC0 (volatile unsigned char*)(0x25) /* timer A channel 0 status/ctrl */ #define TACH0HL (*(volatile unsigned short*)(0x26)) /* timer A channel 0 high and low*/ #define pTACH0HL (volatile unsigned short*)(0x26) /* timer A channel 0 high and low*/ #define TACH0H (*(volatile unsigned char*)(0x26)) /* timer A channel 0 high */ #define pTACH0H (volatile unsigned char*)(0x26) /* timer A channel 0 high */ #define TACH0L (*(volatile unsigned char*)(0x27)) /* timer A channel 0 low */ #define pTACH0L (volatile unsigned char*)(0x27) /* timer A channel 0 low */ #define TASC1 (*(volatile unsigned char*)(0x28)) /* timer A channel 1 status/ctrl */ #define pTASC1 (volatile unsigned char*)(0x28) /* timer A channel 1 status/ctrl */ #define TACH1HL (*(volatile unsigned short*)(0x29)) /* timer A channel 1 high and low*/ #define pTACH1HL (volatile unsigned short*)(0x29) /* timer A channel 1 high and low*/ #define TACH1H (*(volatile unsigned char*)(0x29)) /* timer A channel 1 high */ #define pTACH1H (volatile unsigned char*)(0x29) /* timer A channel 1 high */ #define TACH1L (*(volatile unsigned char*)(0x2A)) /* timer A channel 1 low */ #define pTACH1L (volatile unsigned char*)(0x2A) /* timer A channel 1 low */ /* B TIMER section */ #define TBSC (*(volatile unsigned char*)(0x2B)) /* timer B status/ctrl register */ #define pTBSC (volatile unsigned char*)(0x2B) /* timer B status/ctrl register */ #define TBCNTH (*(volatile unsigned char*)(0x2C)) /* timer B counter high */ #define pTBCNTH (volatile unsigned char*)(0x2C) /* timer B counter high */ #define TBCNTL (*(volatile unsigned char*)(0x2D)) /* timer B counter low */ #define pTBCNTL (volatile unsigned char*)(0x2D) /* timer B counter low */ #define TBMODHL (*(volatile unsigned short*)(0x2E)) /* timer B modulo high */ #define pTBMODHL (volatile unsigned short*)(0x2E) /* timer B modulo high */ #define TBMODH (*(volatile unsigned char*)(0x2E)) /* timer B modulo high */ #define pTBMODH (volatile unsigned char*)(0x2E) /* timer B modulo high */ #define TBMODL (*(volatile unsigned char*)(0x2F)) /* timer B modulo low */ #define pTBMODL (volatile unsigned char*)(0x2F) /* timer B modulo low */ #define TBSC0 (*(volatile unsigned char*)(0x30)) /* timer B channel 0 status/ctrl*/ #define pTBSC0 (volatile unsigned char*)(0x30) /* timer B channel 0 status/ctrl*/ #define TBCH0H (*(volatile unsigned char*)(0x31)) /* timer B channel 0 high */ #define pTBCH0H (volatile unsigned char*)(0x31) /* timer B channel 0 high */ #define TBCH0L (*(volatile unsigned char*)(0x32)) /* timer B channel 0 low */ #define pTBCH0L (volatile unsigned char*)(0x32) /* timer B channel 0 low */ #define TBSC1 (*(volatile unsigned char*)(0x33)) /* timer B channel 1 status/ctrl */ #define pTBSC1 (volatile unsigned char*)(0x33) /* timer B channel 1 status/ctrl */ #define TBCH1H (*(volatile unsigned char*)(0x34)) /* timer B channel 1 high */ #define pTBCH1H (volatile unsigned char*)(0x34) /* timer B channel 1 high */ #define TBCH1L (*(volatile unsigned char*)(0x35)) /* timer B channel 1 low */ #define pTBCH1L (volatile unsigned char*)(0x35) /* timer B channel 1 low */ /* PLL section */ #define PCTL (*(volatile unsigned char*)(0x36)) /* PLL control register */ #define pPCTL (volatile unsigned char*)(0x36) /* PLL control register */ #define PBWC (*(volatile unsigned char*)(0x37)) /* PLL bandwidth register */ #define pPBWC (volatile unsigned char*)(0x37) /* PLL bandwidth register */ #define PMSHL (*(volatile unsigned char*)(0x38)) /* PLL multiplier select high/low register */ #define pPMSHL (volatile unsigned char*)(0x38) /* PLL multiplier select high/low register */ #define PMSH (*(volatile unsigned char*)(0x38)) /* PLL multiplier select high register */ #define pPMSH (volatile unsigned char*)(0x38) /* PLL multiplier select high register */ #define PMSL (*(volatile unsigned char*)(0x39)) /* PLL multiplier select low register */ #define pPMSL (volatile unsigned char*)(0x39) /* PLL multiplier select low register */ #define PMRS (*(volatile unsigned char*)(0x3A)) /* PLL VCO select range register */ #define pPMRS (volatile unsigned char*)(0x3A) /* PLL VCO select range register */ #define PMDS (*(volatile unsigned char*)(0x3B)) /* PLL reference divider register */ #define pPMDS (volatile unsigned char*)(0x3B) /* PLL reference divider register */ /* A/D section */ #define ADSCR (*(volatile unsigned char*)(0x3c)) /* ADC status and control register */ #define pADSCR (volatile unsigned char*)(0x3c) /* ADC status and control register */ #define ADR (*(volatile unsigned char*)(0x3d)) /* ADC data register */ #define pADR (volatile unsigned char*)(0x3d) /* ADC data register */ #define ADCLK (*(volatile unsigned char*)(0x3e)) /* ADC clock register */ #define pADCLK (volatile unsigned char*)(0x3e) /* ADC clock register */ #define RES4 (*(volatile unsigned char*)(0x3f)) /* Unimplemented */ #define pRES4 (volatile unsigned char*)(0x3f) /* Unimplemented */ /* SIM */ #define SBSR (*(volatile unsigned char*)(0xfe00)) /* SIM break status register */ #define pSBSR (volatile unsigned char*)(0xfe00) /* SIM break status register */ #define SRSR (*(volatile unsigned char*)(0xfe01)) /* SIM reset status register */ #define pSRSR (volatile unsigned char*)(0xfe01) /* SIM reset status register */ #define SUBAR (*(volatile unsigned char*)(0xfe02)) /* SIM upper byte address register */ #define pSUBAR (volatile unsigned char*)(0xfe02) /* SIM upper byte address register */ #define SBFCR (*(volatile unsigned char*)(0xfe03)) /* SIM break flag control register */ #define pSBFCR (volatile unsigned char*)(0xfe03) /* SIM break flag control register */ #define INT1 (*(volatile unsigned char*)(0xfe04)) /* Interrupt status register 1 */ #define pINT1 (volatile unsigned char*)(0xfe04) /* Interrupt status register 1 */ #define INT2 (*(volatile unsigned char*)(0xfe05)) /* Interrupt status register 2 */ #define pINT2 (volatile unsigned char*)(0xfe05) /* Interrupt status register 2 */ #define INT3 (*(volatile unsigned char*)(0xfe06)) /* Interrupt status register 3 */ #define pINT3 (volatile unsigned char*)(0xfe06) /* Interrupt status register 3 */ #define RES5 (*(volatile unsigned char*)(0xfe07)) /* Unimplemented */ #define pRES5 (volatile unsigned char*)(0xfe07) /* Unimplemented */ /* FLASH section*/ #define FLCR (*(volatile unsigned char*)(0xfe08)) /*flash control register */ #define pFLCR (volatile unsigned char*)(0xfe08) /*flash control register */ /*BREAK MODE*/ #define BRKH (*(volatile unsigned char*)(0xfe09)) /* SIM reset status register */ #define pBRKH (volatile unsigned char*)(0xfe09) /* SIM reset status register */ #define BRKL (*(volatile unsigned char*)(0xfe0a)) /* SIM reset status register */ #define pBRKL (volatile unsigned char*)(0xfe0a) /* SIM reset status register */ #define BRKSCR (*(volatile unsigned char*)(0xfe0b)) /* SIM reset status register */ #define pBRKSCR (volatile unsigned char*)(0xfe0b) /* SIM reset status register */ #define LVISR (*(volatile unsigned char*)(0xfe0c)) /* LVI status register */ #define pLVISR (volatile unsigned char*)(0xfe0c) /* LVI status register */ #define FLBPR (*(volatile unsigned char*)(0xff7e)) /*block protect register */ #define pFLBPR (volatile unsigned char*)(0xff7e) /*block protect register */ #define COPCTL (*(volatile unsigned char*)(0xffff)) /* COP control register */ #define pCOPCTL (volatile unsigned char*)(0xffff) /* COP control register */ /* CAN section */ #define CAN_BASE ((volatile unsigned char*)0x0500) #define CANMCR0 CAN_BASE[0x0] #define CANMCR1 CAN_BASE[0x1] #define CANBTR0 CAN_BASE[0x2] #define CANBTR1 CAN_BASE[0x3] #define CANRFLG CAN_BASE[0x4] #define CANRIER CAN_BASE[0x5] #define CANTFLG CAN_BASE[0x6] #define CANTCR CAN_BASE[0x7] #define CANIDAC CAN_BASE[0x8] #define CANRXERR CAN_BASE[0xE] #define CANTXERR CAN_BASE[0xF] #define CANIDAR0 CAN_BASE[0x10] #define CANIDAR1 CAN_BASE[0x11] #define CANIDAR2 CAN_BASE[0x12] #define CANIDAR3 CAN_BASE[0x13] #define CANIDMR0 CAN_BASE[0x14] #define CANIDMR1 CAN_BASE[0x15] #define CANIDMR2 CAN_BASE[0x16] #define CANIDMR3 CAN_BASE[0x17] #define CAN_IDR0 CAN_BASE[0xb0] #define CAN_IDR1 CAN_BASE[0xb1] #define CAN_IDR2 CAN_BASE[0xb2] #define CAN_IDR3 CAN_BASE[0xb3] #define CAN_DSR0 CAN_BASE[0xb4] #define CAN_DSR1 CAN_BASE[0xb5] #define CAN_DSR2 CAN_BASE[0xb6] #define CAN_DSR3 CAN_BASE[0xb7] #define CAN_DSR4 CAN_BASE[0xb8] #define CAN_DSR5 CAN_BASE[0xb9] #define CAN_DSR6 CAN_BASE[0xbA] #define CAN_DSR7 CAN_BASE[0xbB] #define CAN_DLR CAN_BASE[0xbC] #define CAN_TBPR CAN_BASE[0xbD]