;**************************************************************************************** ;* Title: HC908QY4.equ Copyright (c) Motorola 2002 ;**************************************************************************************** ;* Author: Kazue Kikuchi ;* ;* Description: Register and bit name definitions for MC68HC908QY4 and MC68HC908QT4 ;* ;* Documentation: MC68HC908QT4/D Advance Information ;* Include Files: none ;* ;* Assembler: P&E Microcomputer Systems - CASM08Z (v3.16) ;* ;* Revision History: ;* Rev # Date Who Comments ;* ------ ----------- ------ ----------------------------------------------------- ;* ES 1.0 29-Apr-02 KK Initial release ;* ES 1.1 07-Jun-02 KK Fixed OSCTRIM address and typos ;* ES 1.2 22-July-02 DG Fixed ; Typo ;* ;**************************************************************************************** ;**************************************************************************************** ;* ;* Motorola reserves the right to make changes without further notice to any product ;* herein to improve reliability, function, or design. Motorola does not assume any ;* liability arising out of the application or use of any product, circuit, or software ;* described herein; neither does it convey any license under its patent rights nor the ;* rights of others. Motorola products are not designed, intended, or authorized for ;* use as components in systems intended for surgical implant into the body, or other ;* applications intended to support life, or for any other application in which the ;* failure of the Motorola product could create a situation where personal injury or ;* death may occur. Should Buyer purchase or use Motorola products for any such ;* intended or unauthorized application, Buyer shall indemnify and hold Motorola and ;* its officers, employees, subsidiaries, affiliates, and distributors harmless against ;* all claims, costs, damages, and expenses, and reasonable attorney fees arising out ;* of, directly or indirectly, any claim of personal injury or death associated with ;* such unintended or unauthorized use, even if such claim alleges that Motorola was ;* negligent regarding the design or manufacture of the part. ;* ;* Motorola and the Motorola logo are registered trademarks of Motorola, Inc. ;**************************************************************************************** ;**** Memory Map and Interrupt Vectors ************************************************ ;* RamStart: equ $0080 ;Start of RAM RamLast: equ $00FF ;Last RAM location FlashStart: equ $EE00 ;Start of Flash FlashLast: equ $FDFF ;Last Flash location ; Vadc: equ $FFDE ;ADC vector Vkbd: equ $FFE0 ;Keyboard vector Vtimov: equ $FFF2 ;Timer overflow vector Vtimch1: equ $FFF4 ;Timer channel 1 vector Vtimch0: equ $FFF6 ;Timer channel 0 vector Virq: equ $FFFA ;IRQ vector Vswi: equ $FFFC ;SWI vector Vreset: equ $FFFE ;Reset vector ;**** Input/Output (I/O) Ports ******************************************************* ;* PTA: equ $00 ;Port A data register ; bit numbers for use in BLCR, BSET, BRCLR, and BRSET AWUL equ 6 ;Auto wake-up latch data PTA5: equ 5 ;Port A data bit 5 PTA4: equ 4 ;Port A data bit 4 PTA3: equ 3 ;Port A data bit 3 PTA2: equ 2 ;Port A data bit 2 PTA1: equ 1 ;Port A data bit 1 PTA0: equ 0 ;Port A data bit 0 ; bit position masks mAWUL: equ %01000000 ;Auto wake-up latch data mPTA5: equ %00100000 ;Port A data bit 5 mPTA4: equ %00010000 ;Port A data bit 4 mPTA3: equ %00001000 ;Port A data bit 3 mPTA2: equ %00000100 ;Port A data bit 2 mPTA1: equ %00000010 ;Port A data bit 1 mPTA0: equ %00000001 ;Port A data bit 0 PTB: equ $01 ;Port B data register ; bit numbers for use in BLCR, BSET, BRCLR, and BRSET PTB7: equ 7 ;Port B data bit 7 PTB6: equ 6 ;Port B data bit 6 PTB5: equ 5 ;Port B data bit 5 PTB4: equ 4 ;Port B data bit 4 PTB3: equ 3 ;Port B data bit 3 PTB2: equ 2 ;Port B data bit 2 PTB1: equ 1 ;Port B data bit 1 PTB0: equ 0 ;Port B data bit 0 ; bit position masks mPTB7: equ %10000000 ;Port B data bit 7 mPTB6: equ %01000000 ;Port B data bit 6 mPTB5: equ %00100000 ;Port B data bit 5 mPTB4: equ %00010000 ;Port B data bit 4 mPTB3: equ %00001000 ;Port B data bit 3 mPTB2: equ %00000100 ;Port B data bit 2 mPTB1: equ %00000010 ;Port B data bit 1 mPTB0: equ %00000001 ;Port B data bit 0 DDRA: equ $04 ;Port A data direction register ; bit numbers for use in BLCR, BSET, BRCLR, and BRSET DDRA5: equ 5 ;Port A data direction bit 5 DDRA4: equ 4 ;Port A data direction bit 4 DDRA3: equ 3 ;Port A data direction bit 3 DDRA1: equ 1 ;Port A data direction bit 1 DDRA0: equ 0 ;Port A data direction bit 0 ; bit position masks mDDRA5: equ %00100000 ;Port A data direction bit 5 mDDRA4: equ %00010000 ;Port A data direction bit 4 mDDRA3: equ %00001000 ;Port A data direction bit 3 mDDRA1: equ %00000010 ;Port A data direction bit 1 mDDRA0: equ %00000001 ;Port A data direction bit 0 DDRB: equ $05 ;Port B data direction register ; bit numbers for use in BLCR, BSET, BRCLR, and BRSET DDRB7: equ 7 ;Port B data direction bit 7 DDRB6: equ 6 ;Port B data direction bit 6 DDRB5: equ 5 ;Port B data direction bit 5 DDRB4: equ 4 ;Port B data direction bit 4 DDRB3: equ 3 ;Port B data direction bit 3 DDRB2: equ 2 ;Port B data direction bit 2 DDRB1: equ 1 ;Port B data direction bit 1 DDRB0: equ 0 ;Port B data direction bit 0 ; bit position masks mDDRB7: equ %10000000 ;Port B data direction bit 7 mDDRB6: equ %01000000 ;Port B data direction bit 6 mDDRB5: equ %00100000 ;Port B data direction bit 5 mDDRB4: equ %00010000 ;Port B data direction bit 4 mDDRB3: equ %00001000 ;Port B data direction bit 3 mDDRB2: equ %00000100 ;Port B data direction bit 2 mDDRB1: equ %00000010 ;Port B data direction bit 1 mDDRB0: equ %00000001 ;Port B data direction bit 0 PTAPUE: equ $0B ;Port A input pullup enable register ; bit numbers for use in BLCR, BSET, BRCLR, and BRSET OSC2EN: equ 7 ;OSC2 pin enable PTAPUE5: equ 5 ;Port A input pull up enable bit 5 PTAPUE4: equ 4 ;Port A input pull up enable bit 4 PTAPUE3: equ 3 ;Port A input pull up enable bit 3 PTAPUE2: equ 2 ;Port A input pull up enable bit 2 PTAPUE1: equ 1 ;Port A input pull up enable bit 1 PTAPUE0: equ 0 ;Port A input pull up enable bit 0 ; bit position masks mOSC2EN: equ %10000000 ;OSC2 pin enable mPTAPUE5: equ %00100000 ;Port A input pull up enable bit 5 mPTAPUE4: equ %00010000 ;Port A input pull up enable bit 4 mPTAPUE3: equ %00001000 ;Port A input pull up enable bit 3 mPTAPUE2: equ %00000100 ;Port A input pull up enable bit 2 mPTAPUE1: equ %00000010 ;Port A input pull up enable bit 1 mPTAPUE0: equ %00000001 ;Port A input pull up enable bit 0 PTBPUE: equ $0C ;Port B input pullup enable register ; bit numbers for use in BLCR, BSET, BRCLR, and BRSET PTBPUE7: equ 7 ;Port B input pull up enable bit 7 PTBPUE6: equ 6 ;Port B input pull up enable bit 6 PTBPUE5: equ 5 ;Port B input pull up enable bit 5 PTBPUE4: equ 4 ;Port B input pull up enable bit 4 PTBPUE3: equ 3 ;Port B input pull up enable bit 3 PTBPUE2: equ 2 ;Port B input pull up enable bit 2 PTBPUE1: equ 1 ;Port B input pull up enable bit 1 PTBPUE0: equ 0 ;Port B input pull up enable bit 0 ; bit position masks mPTBPUE7: equ %10000000 ;Port B input pull up enable bit 7 mPTBPUE6: equ %01000000 ;Port B input pull up enable bit 6 mPTBPUE5: equ %00100000 ;Port B input pull up enable bit 5 mPTBPUE4: equ %00010000 ;Port B input pull up enable bit 4 mPTBPUE3: equ %00001000 ;Port B input pull up enable bit 3 mPTBPUE2: equ %00000100 ;Port B input pull up enable bit 2 mPTBPUE1: equ %00000010 ;Port B input pull up enable bit 1 mPTBPUE0: equ %00000001 ;Port B input pull up enable bit 0 ;**** Keyboard Interrupt Module (KBI) ************************************************* ;* KBSCR: equ $1A ;Keyboard status and control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET KEYF: equ 3 ;Keyboard flag ACKK: equ 2 ;Keyboard acknowledge IMASKK: equ 1 ;Keyboard interrupt mask MODEK: equ 0 ;Keyboard triggering sesitivity ; bit position masks mKEYF: equ %00001000 ;Keyboard flag mACKK: equ %00000100 ;Keyboard acknowledge mIMASKK: equ %00000010 ;Keyboard interrupt mask mMODEK: equ %00000001 ;Keyboard triggering sesitivity KBIER: equ $1B ;Keyboard interrupt enable register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET AWUIE: equ 6 ;Auto wake-up interrupt enable KBIE5: equ 5 ;Port A keyboard interrupt enable bit 5 KBIE4: equ 4 ;Port A keyboard interrupt enable bit 4 KBIE3: equ 3 ;Port A keyboard interrupt enable bit 3 KBIE2: equ 2 ;Port A keyboard interrupt enable bit 2 KBIE1: equ 1 ;Port A keyboard interrupt enable bit 1 KBIE0: equ 0 ;Port A keyboard interrupt enable bit 0 ; bit position masks mAWUIE equ %01000000 ;Auto wake-up interrupt enable mKBIE5: equ %00100000 ;Port A keyboard interrupt enable bit 5 mKBIE4: equ %00010000 ;Port A keyboard interrupt enable bit 4 mKBIE3: equ %00001000 ;Port A keyboard interrupt enable bit 3 mKBIE2: equ %00000100 ;Port A keyboard interrupt enable bit 2 mKBIE1: equ %00000010 ;Port A keyboard interrupt enable bit 1 mKBIE0: equ %00000001 ;Port A keyboard interrupt enable bit 0 ;**** External Interrupt (IRQ) ******************************************************** ;* INTSCR: equ $1D ;IRQ status and control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET IRQF1: equ 3 ;IRQ flag ACK1: equ 2 ;IRQ interrupt request acknowledge IMASK1: equ 1 ;IRQ interrupt mask MODE1: equ 0 ;IRQ edge/level select ; bit position masks mIRQF1: equ %00001000 ;IRQ flag mACK1: equ %00000100 ;IRQ interrupt request acknowledge mIMASK1: equ %00000010 ;IRQ interrupt mask mMODE1: equ %00000001 ;IRQ edge/level select ;**** Configuration Registers (CONFIG) ************************************************* ;* CONFIG2: equ $1E ;Configuration register 2 ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET IRQPUD: equ 7 ;IRQ pin pullup control IRQEN: equ 6 ;IRQ pin function selection OSCOPT1: equ 4 ;Selection bit 1 for oscillator option OSCOPT0: equ 3 ;Selection bit 0 for oscillator option RSTEN: equ 0 ;RST pin function selection ; bit position masks mIRQPUD: equ %10000000 ;IRQ pin pullup control mIRQEN: equ %01000000 ;IRQ pin function selection mOSCOPT1: equ %00010000 ;Selection bit 1 for oscillator option mOSCOPT0: equ %00001000 ;Selection bit 0 for oscillator option mRSTEN: equ %00000001 ;RST pin function selection CONFIG1: equ $1F ;Configuration register 1 ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET COPRS: equ 7 ;COP reset period selection LVISTOP: equ 6 ;LVI enable in stop mode LVIRSTD: equ 5 ;LVI reset disable LVIPWRD: equ 4 ;LVI power disable LVI5OR3: equ 3 ;LVI 5V or 3V operating mode SSREC: equ 2 ;Short stop recovery STOP: equ 1 ;STOP instruction enable COPD: equ 0 ;COP disable ; bit position masks mCOPRS: equ %10000000 ;COP reset period selection mLVISTOP: equ %01000000 ;LVI enable in stop mode mLVIRSTD: equ %00100000 ;LVI reset disable mLVIPWRD: equ %00010000 ;LVI power disable mLVI5OR3: equ %00001000 ;LVI 5V or 3V operating mode mSSREC: equ %00000100 ;Short stop recovery mSTOP: equ %00000010 ;STOP instruction enable mCOPD: equ %00000001 ;COP disable ;**** Timer Interface module (TIM) **************************************************** ;* TSC: equ $20 ;Timer status and control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET TOF: equ 7 ;TIM overflow flag TOIE: equ 6 ;TIM overflow interrupt enable TSTOP: equ 5 ;TIM Stop bit TRST: equ 4 ;TIM Reset bit PS2: equ 2 ;Prescaler select bit 2 PS1: equ 1 ;Prescaler select bit 1 PS0: equ 0 ;Prescaler select bit 0 ; bit position masks mTOF: equ %10000000 ;TIM overflow flag mTOIE: equ %01000000 ;TIM overflow interrupt enable mTSTOP: equ %00100000 ;TIM Stop bit mTRST: equ %00010000 ;TIM Reset bit mPS2: equ %00000100 ;Prescaler select bit 2 mPS1: equ %00000010 ;Prescaler select bit 1 mPS0: equ %00000001 ;Prescaler select bit 0 TSC0: equ $25 ;Timer channel 0 status and control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET CH0F: equ 7 ;Channel 0 flag CH0IE: equ 6 ;Channel 0 interrupt enable MS0B: equ 5 ;Mode select bit B MS0A: equ 4 ;Mode select bit A ELS0B: equ 3 ;Edge/level select bit B ELS0A: equ 2 ;Edge/level select bit A TOV0 equ 1 ;Toggle on overflow CH0MAX equ 0 ;Channel 0 maximum duty cycle ; bit position masks mCH0F: equ %10000000 ;Channel 0 flag mCH0IE: equ %01000000 ;Channel 0 interrupt enable mMS0B: equ %00100000 ;Mode select bit B mMS0A: equ %00010000 ;Mode select bit A mELS0B: equ %00001000 ;Edge/level select bit B mELS0A: equ %00000100 ;Edge/level select bit A mTOV0 equ %00000010 ;Toggle on overflow mCH0MAX equ %00000001 ;Channel 0 maximum duty cycle TSC1: equ $28 ;Timer channel 1 status and control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET CH1F: equ 7 ;Channel 1 flag CH1IE: equ 6 ;Channel 1 interrupt enable MS1B: equ 5 ;Mode select bit B MS1A: equ 4 ;Mode select bit A ELS1B: equ 3 ;Edge/level select bit B ELS1A: equ 2 ;Edge/level select bit A TOV1 equ 1 ;Toggle on overflow CH1MAX equ 0 ;Channel 1 maximum duty cycle ; bit position masks mCH1F: equ %10000000 ;Channel 1 flag mCH1IE: equ %01000000 ;Channel 1 interrupt enable mMS1B: equ %00100000 ;Mode select bit B mMS1A: equ %00010000 ;Mode select bit A mELS1B: equ %00001000 ;Edge/level select bit B mELS1A: equ %00000100 ;Edge/level select bit A mTOV1 equ %00000010 ;Toggle on overflow mCH1MAX equ %00000001 ;Channel 1 maximum duty cycle TCNTH: equ $21 ;Timer counter register high TCNTL: equ $22 ;Timer counter register Low TMODH: equ $23 ;Timer counter modulo register high TMODL: equ $24 ;Timer counter modulo register low TCH0H: equ $26 ;Timer channel 0 register high TCH0L: equ $27 ;Timer channel 0 register low TCH1H: equ $29 ;Timer channel 1 register high TCH1L: equ $2A ;Timer channel 1 register low ;**** Oscillator Module (OSC) *************************************************** ;* OSCSTAT: equ $36 ;Oscillator status register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET ECGON: equ 1 ;External clock generator on ECGST: equ 0 ;External clock status ; bit position masks mECGON: equ %00000010 ;External clock generator on mECGST: equ %00000001 ;External clock status OSCTRIM: equ $38 ;Oscillator trim register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET TRIM7: equ 7 ;Internal oscillator trim factor bit 7 TRIM6: equ 6 ;Internal oscillator trim factor bit 6 TRIM5: equ 5 ;Internal oscillator trim factor bit 5 TRIM4: equ 4 ;Internal oscillator trim factor bit 4 TRIM3: equ 3 ;Internal oscillator trim factor bit 3 TRIM2: equ 2 ;Internal oscillator trim factor bit 2 TRIM1: equ 1 ;Internal oscillator trim factor bit 1 TRIM0: equ 0 ;Internal oscillator trim factor bit 0 ; bit position masks mTRIM7: equ %10000000 ;Internal oscillator trim factor bit 7 mTRIM6: equ %01000000 ;Internal oscillator trim factor bit 6 mTRIM5: equ %00100000 ;Internal oscillator trim factor bit 5 mTRIM4: equ %00010000 ;Internal oscillator trim factor bit 4 mTRIM3: equ %00001000 ;Internal oscillator trim factor bit 3 mTRIM2: equ %00000100 ;Internal oscillator trim factor bit 2 mTRIM1: equ %00000010 ;Internal oscillator trim factor bit 1 mTRIM0: equ %00000001 ;Internal oscillator trim factor bit 0 TRIMLOC: equ $FFC0 ;Internal oscillator trim value ;**** Analog-to-Digital Converter (ADC) *********************************************** ;* ADSCR: equ $3C ;ADC status and control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET COCO: equ 7 ;Conversions complete AIEN: equ 6 ;ADC interrupt enable bit ADCO: equ 5 ;ADC continuous conversion CH4: equ 4 ;ADC channel select bit 4 CH3: equ 3 ;ADC channel select bit 3 CH2: equ 2 ;ADC channel select bit 2 CH1: equ 1 ;ADC channel select bit 1 CH0: equ 0 ;ADC channel select bit 0 ; bit position masks mCOCO: equ %10000000 ;Conversions complete mAIEN: equ %01000000 ;ADC interrupt enable bit mADCO: equ %00100000 ;ADC continuous conversion mCH4: equ %00010000 ;ADC channel select bit 4 mCH3: equ %00001000 ;ADC channel select bit 3 mCH2: equ %00000100 ;ADC channel select bit 2 mCH1: equ %00000010 ;ADC channel select bit 1 mCH0: equ %00000001 ;ADC channel select bit 0 ADR: equ $3E ;ADC data register ADICLK: equ $3F ;ADC input clock register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET ADIV2: equ 7 ;ADC clock prescaler bit 2 ADIV1: equ 6 ;ADC clock prescaler bit 1 ADIV0: equ 5 ;ADC clock prescaler bit 0 ; bit position masks mADIV2: equ %10000000 ;ADC clock prescaler bit 2 mADIV1: equ %01000000 ;ADC clock prescaler bit 1 mADIV0: equ %00100000 ;ADC clock prescaler bit 0 ;**** System Integration Module (SIM) ************************************************* ;* BSR: equ $FE00 ;SIM break status register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET SBSW equ 1 ;SIM break stop/wait ; bit position masks mSBSW: equ %00000010 ;SIM break stop/wait SRSR: equ $FE01 ;SIM reset status register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET POR: equ 7 ;Power-on reset PIN: equ 6 ;External reset COP: equ 5 ;COP reset ILOP: equ 4 ;Illegal opcode reset ILAD: equ 3 ;Illegal address reset MODRST: equ 2 ;Monitor mode entry module reset LVI: equ 1 ;LVI reset ; bit position masks mPOR: equ %10000000 ;Power-on reset mPIN: equ %01000000 ;External reset mCOP: equ %00100000 ;COP reset mILOP: equ %00010000 ;Illegal opcode reset mILAD: equ %00001000 ;Illegal address reset mMODRST: equ %00000100 ;Monitor mode entry module reset mLVI: equ %00000010 ;LVI reset BRKAR: equ $FE02 ;Break auxiliary register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET BDCOP: equ 0 ;Break disable COP ; bit position masks mBDCOP: equ %00000001 ;Break disable COP BFCR: equ $FE03 ;Break flag control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET BCFE: equ 7 ;Break clear flag enable ; bit position masks mBCFE: equ %10000000 ;Break clear flag enable INT1: equ $FE04 ;Interrupt status register 1 ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET IF5: equ 6 ;Interrupt flag 5 IF4: equ 5 ;Interrupt flag 4 IF3: equ 4 ;Interrupt flag 3 IF1: equ 2 ;Interrupt flag 1 INT2: equ $FE05 ;Interrupt status register 2 ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET IF14: equ 7 ;Interrupt flag 14 INT3: equ $FE06 ;Interrupt status register 3 ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET IF15: equ 0 ;Interrupt flag 15 ;**** Flash Memory ******************************************************************** ;* FLCR: equ $FE08 ;Flash control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET HVEN: equ 3 ;High-voltage enable bit mask MASS: equ 2 ;Mass erase control bit mask ERASE: equ 1 ;Erase control bit mask PGM: equ 0 ;Program control bit mask ; bit position masks mHVEN: equ %00001000 ;High-voltage enable bit mask mMASS: equ %00000100 ;Mass erase control bit mask mERASE: equ %00000010 ;Erase control bit mask mPGM: equ %00000001 ;Program control bit mask FLBPR: equ $FFBE ;Flash block protect register ;**** Breakpoint Module (BRK) ********************************************************* ;* BRKH: equ $FE09 ;Break address register high BRKL: equ $FE0A ;Break address register low BRKSCR: equ $FE0B ;Break status and control register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET BRKE: equ 7 ;Break enable BRKA: equ 6 ;Break active ; bit position masks mBRKE: equ %10000000 ;Break enable mBRKA: equ %01000000 ;Break active ;**** Low-Voltage Inhibit (LVI) ******************************************************* ;* LVISR: equ $FE0C ;LVI status register ; bit numbers for use in BCLR, BSET, BRCLR, and BRSET LVIOUT: equ 7 ;LVI output bit ; bit position masks mLVIOUT: equ %10000000 ;LVI output bit ;**** Computer Operating Properly (COP) *********************************************** ;* COPCTL: equ $FFFF ;COP control register